Introduction to VLSI Design - Electronics zone

Introduction to VLSI Design - Electronics zone

Complete ASIC Design Flow: VLSI From Idea to Silicon Introduction to VLSI Design

Complete ASIC Design Flow: VLSI From Idea to Silicon

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Introduction To Digital Circuits

Introduction To Digital Circuits

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Digital logic Families

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Bipolar logic Families

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MOS logic Family

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CMOS logic Family

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Digital Logic Gates

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Verilog HDL : From Syntax to Complex Systems

Introduction to VLSI Design

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Introduction to Digital Careers (ASIC Flow)

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Introduction to Verilog HDL

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Structure of Verilog Module & Interface Declaration

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Always block & Sensitivity List

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Blocking & non Blocking Assignment

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Assignment 1.0 Design your first circuit

Lab 2.0 Assignments

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If/else statement

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Continuous assignment

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Lab 2.1 Counter RTL

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Numbers in Verilog

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Inter Assignment Delays, Clock Generator & Initial block

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Lab 3.0 Counter RTL & Testbench

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Countinue Lab 3.0 simulating with Testbench

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Assignment 2.0 Design Up Down Counter and its Testbench

Case statement with Decoders/Encoders Application

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Verilog Operators - Bitwise, Conditional, Arithmetic, and Logical

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Operators - Shift, Equality/Relational, and Miscellaneous

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Assignment 3.0 Design 16-bit ALU

Unintentional Latch

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Simulation Race

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Flip-Flops in Verilog - Implementation, Reset, and Preset

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Structural Verilog

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Lab 4.1 Top Module Design

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Parameterized Design and Multidimensional Arrays in Verilog

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Assignment 4.0 Design Top Module for 16-bit ALU

Assignment 4.1 Verilog Design of 8 x 16 Register File

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For Loop and the Combinational Loop

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Lab 5.0 designing LFSR

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Lab 5.0 Testbench for LFSR

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Finite State Machine (FSM)

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Lab 5.1 Writing FSM Mealy

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Lab 5.1 Writing FSM Moore

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Timing Control & Forever loop

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Assignment 5.0 Design Linear Feedback Shift Register

Assignment 5.1 Design Automatic Garage Door Controller

TCL Scripting for Writing Constraints

TCL Scripting Introduction and first command

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TCL expr Command

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Backslash, Grouping, String, and Append Command

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Downloading Tcl_shell

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Flow Control and Lists

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List Manipulation, Loops and Arrays

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Continue with Arrays and Procedures

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File Handling and RegSub Command

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Timing Analysis Foundations: STA Concepts, Analysis & Fixes

The Bedrock of Digital Design: Latches & Flip-Flops

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The Path of a Signal: Combinational & Sequential Timing Arcs

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The Imperfect Clock: Skew and Jitter

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The Setup Time Check - Catching the Bus

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Setup Time Analysis Lab

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Fixing Violations & The Critical Path

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Assignment Setup/Hold Analysis

Fundamentals of Low-Power VLSI Design

Understanding Power Consumption

Glitch Power - The Unnecessary Work

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Switching Power - The Main Battery Drain

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Short-Circuit Power - The Brief Short

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Leakage Power - The Silent Battery Killer

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Clock Gating - The Ultimate Power Saver

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LAB : Designing a Clock Gate in Verilog HDL

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Operand Isolation - Freezing the Data

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Multi-Voltage Domains - Right-Sizing Power

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Multiple Frequencies Technique or Frequency Scaling

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Power Equation Deep Dive

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Multi Threshold (MVT) Voltage

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Power Gating - The Nuclear Option

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Final Power aware design Assignment

Starting On the Project : Designing UART

VLSI Logic Synthesis : From RTL to Gate-Level Netlist

Introduction to Synthesis

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Libraries Definition (.LIB .LEF .GDS)

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Operating Condition (Worst, Best & Typical)

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Reading Design Files

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Compile & Generate Gate Level Netlist

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Timing Analysis (Dynamic & Static analysis)

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Design Environment Constraints

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Design Optimization Constraints

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Timing Exceptions Constraints

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Clock Grouping & Case Analysis Constraints

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Reporting (Area, Power, Timing)

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Clock Domain Crossing (CDC) & FIFO Design

Introduction to CDC

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Problem 1: Metastability

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Solution: Bit synchronization Techniques

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Problem 2: Data Incoherence

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Solution: Bus synchronization Techniques

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Problem 3: Data Loss

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Bit Synchronizer Design using Verilog LAB

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Data Synchronizer Assignment

Solution: Asynchronous FIFO

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Challenge 1: Asynchronous FIFO

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Challenge 2: Asynchronous FIFO

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FIFO -> Depth Calculation

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FIFO Depth Calculation LAB

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Asynchronous FIFO Assignment

Reset synchronizer

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Reset Synchronizer Asssignment

Design for Test (DFT)

Introduction & Manufacturing Test Vs Functional Test

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Controllability and Observability

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ShiftIn & Capture & ShiftOut

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DFT Constraints

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Assignment_DFT_1.0

Formal Verification : Synopsys Formality Flow & Debug

Introduction to Formal Verification

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Formal Verification Components & Design Equivalence Checking

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Lab1 Formal Verification

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Lab2 Formal Verification

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Lab3 Formal Verification

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Intro to debugging

Debugging Cases

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Assignment_Formal 1.0

Assignment_Formal 2.0

Final System Assignment

Final system Assignment

Final system Assignment Solution

Physical Design: PnR with Cadence

Place & Route Flow

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I/O Placement & Specify Floorplan

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Timing Analysis & Timing Optimization

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Clock Tree Synthesis & Routing

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Final Practical PnR Lab using Cadence and exporting GDS

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Final System Assignment PnR

Final System Assignment PnR

Announcements Reviews Live Classes Certificate Course Info

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