Complete ASIC Design Flow: VLSI From Idea To Silicon

About Course

Full Digital IC Design Flow: Verilog, Synthesis, DFT, CDC, Low‑Power, & PnR with Cadence & Synopsys

No prior VLSI experience? No problem. This course is designed to take you from absolute beginner to an engineer capable of designing a complete, complex system chip—all the way from digital logic to a tape‑out ready GDSII file.

Most courses teach isolated pieces: a bit of Verilog, some timing, or a tool. This one is different. We walk you through the entire ASIC design flow in a structured, step‑by‑step way, assuming no background in chip design. You’ll start by understanding what a transistor is and how digital circuits work. Then, you’ll learn Verilog HDL through dozens of labs and assignments, progressing from simple counters to a 16‑bit ALU, register files, and finite state machines.

But front‑end RTL is only the beginning. We then dive into the critical implementation stages: TCL scripting to automate flows, Static Timing Analysis (STA) to fix setup/hold violations, low‑power design techniques used in modern mobile chips, and logic synthesis where RTL is transformed into gates. You’ll also master Clock Domain Crossing (CDC) with asynchronous FIFOs, Design for Test (DFT) with scan chains, and formal verification to ensure equivalence.

All of this culminates in a final system assignment—a UART‑based subsystem with a register file and ALU, which you then take through the physical design (PnR) flow using Cadence tools, ending with GDSII export. By the end, you will have built a chip from the ground up, with a portfolio project that proves your skills.

Digital Fundamentals: From CMOS logic families and gate‑level behavior to delay and power (dynamic, leakage).
Verilog HDL: Write RTL for counters, ALUs, FSMs, register files, and testbenches—no prior coding experience needed.
TCL Scripting: Automate constraints and flows—an essential skill for CAD and backend engineers.
Static Timing Analysis (STA): Perform setup/hold analysis, identify critical paths, and fix violations.
Low‑Power Design: Implement clock gating, operand isolation, multi‑VT, and power gating.
Logic Synthesis: Convert RTL to gate‑level netlists using industry‑style constraints and libraries.
Clock Domain Crossing (CDC): Handle metastability, data incoherence, and design asynchronous FIFOs with depth calculation.
Design for Test (DFT): Insert scan chains and improve testability.
Formal Verification: Run equivalence checking with Synopsys Formality.
Physical Design (PnR): Complete floorplanning, power planning, placement, CTS, routing, and chip finishing using Cadence; export GDSII.

Course Content

Introduction To Digital Circuits

Introduction To Digital Circuits
11:48
Digital logic Families
09:19
Bipolar logic Families
16:26
MOS logic Family
14:33
CMOS logic Family
14:26
Delay in CMOS
18:07
Dynamic Power
11:34
Digital Logic Gates
07:49

Verilog HDL : From Syntax to Complex Systems

Introduction to VLSI Design
36:37
Introduction to Digital Careers (ASIC Flow)
31:28
Introduction to Verilog HDL
16:56
Structure of Verilog Module & Interface Declaration
28:15
Always block & Sensitivity List
25:28
Lab 1.0
16:57
Blocking & non Blocking Assignment
22:39
Assignment 1.0 Design your first circuit
Lab 2.0 Assignments
01:55
If/else statement
14:17
Continuous assignment
11:29
Lab 2.1 Counter RTL
23:10
Numbers in Verilog
19:56
Testbenches
23:45
Inter Assignment Delays, Clock Generator & Initial block
25:39
Lab 3.0 Counter RTL & Testbench
40:24
Countinue Lab 3.0 simulating with Testbench
12:25
Assignment 2.0 Design Up Down Counter and its Testbench
Case statement with Decoders/Encoders Application
18:13
Verilog Operators – Bitwise, Conditional, Arithmetic, and Logical
22:46
Operators – Shift, Equality/Relational, and Miscellaneous
23:14
Lab 3.1
05:35
Assignment 3.0 Design 16-bit ALU
Unintentional Latch
26:49
Lab 4.0
14:34
Simulation Race
18:46
Flip-Flops in Verilog – Implementation, Reset, and Preset
30:06
Structural Verilog
13:52
Lab 4.1 Top Module Design
14:12
Parameterized Design and Multidimensional Arrays in Verilog
20:13
Lab 4.2
06:20
Assignment 4.0 Design Top Module for 16-bit ALU
Assignment 4.1 Verilog Design of 8 x 16 Register File
Functions
15:40
Tasks
14:04
For Loop and the Combinational Loop
13:12
Lab 5.0 designing LFSR
27:11
Lab 5.0 Testbench for LFSR
31:13
Finite State Machine (FSM)
25:23
Lab 5.1 Writing FSM Mealy
30:42
Lab 5.1 Writing FSM Moore
12:17
Timing Control & Forever loop
19:00
Lab 5.2
05:28
Assignment 5.0 Design Linear Feedback Shift Register
Assignment 5.1 Design Automatic Garage Door Controller

TCL Scripting for Writing Constraints

Timing Analysis Foundations: STA Concepts, Analysis & Fixes

Fundamentals of Low-Power VLSI Design

Starting On the Project : Designing UART

VLSI Logic Synthesis : From RTL to Gate-Level Netlist

Clock Domain Crossing (CDC) & FIFO Design

Design for Test (DFT)

Formal Verification : Synopsys Formality Flow & Debug

Final System Assignment

Physical Design: PnR with Cadence

Final System Assignment PnR

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About Course

What Will You Learn?

Course Content

Introduction To Digital Circuits

Introduction To Digital Circuits

Digital logic Families

Bipolar logic Families

MOS logic Family

CMOS logic Family

Delay in CMOS

Dynamic Power

Digital Logic Gates

Verilog HDL : From Syntax to Complex Systems

Introduction to VLSI Design

Introduction to Digital Careers (ASIC Flow)

Introduction to Verilog HDL

Structure of Verilog Module & Interface Declaration

Always block & Sensitivity List

Lab 1.0

Blocking & non Blocking Assignment

Assignment 1.0 Design your first circuit

Lab 2.0 Assignments

If/else statement

Continuous assignment

Lab 2.1 Counter RTL

Numbers in Verilog

Testbenches

Inter Assignment Delays, Clock Generator & Initial block

Lab 3.0 Counter RTL & Testbench

Countinue Lab 3.0 simulating with Testbench

Assignment 2.0 Design Up Down Counter and its Testbench

Case statement with Decoders/Encoders Application

Verilog Operators – Bitwise, Conditional, Arithmetic, and Logical

Operators – Shift, Equality/Relational, and Miscellaneous

Lab 3.1

Assignment 3.0 Design 16-bit ALU

Unintentional Latch

Lab 4.0

Simulation Race

Flip-Flops in Verilog – Implementation, Reset, and Preset

Structural Verilog

Lab 4.1 Top Module Design

Parameterized Design and Multidimensional Arrays in Verilog

Lab 4.2

Assignment 4.0 Design Top Module for 16-bit ALU

Assignment 4.1 Verilog Design of 8 x 16 Register File

Functions

Tasks

For Loop and the Combinational Loop

Lab 5.0 designing LFSR

Lab 5.0 Testbench for LFSR

Finite State Machine (FSM)

Lab 5.1 Writing FSM Mealy

Lab 5.1 Writing FSM Moore

Timing Control & Forever loop

Lab 5.2

Assignment 5.0 Design Linear Feedback Shift Register

Assignment 5.1 Design Automatic Garage Door Controller

TCL Scripting for Writing Constraints

TCL Scripting Introduction and first command

TCL expr Command

Backslash, Grouping, String, and Append Command

Downloading Tcl_shell

Lab1.0

Lab1.1

Lab1.2

Assignment_1.0

Assignment_1.1

Assignment_1.2

Flow Control and Lists

List Manipulation, Loops and Arrays

Continue with Arrays and Procedures

Lab2.0

Lab2.1

File Handling and RegSub Command

Lab2.2

Assignment_2.0

Assignment_2.1

Assignment_2.2

Timing Analysis Foundations: STA Concepts, Analysis & Fixes